The principal duties of the main BIOS during POST are as follows:

The BIOS will begin its POST duties when the CPU is reset. The first memory location the CPU tries to execute is known as the reset vector. In the case of a hard reboot, the north-bridge will direct this code fetch (request) to the BIOS located on the system flash memory. For a warm boot, the BIOS will be located in the proper place in RAM and the north-bridge will direct the reset vector call to the RAM.
During the POST flow of a contemporary BIOS, one of the first things a BIOS should do is determine the reason it is executing. For a cold boot, for example, it may need to execute all of its functionality. If, however, the system supports power savings or quick boot methods, the BIOS may be able to circumvent the standard POST device discovery, and simply program the devices from a reloaded system device table.
The POST flow for the PC has developed from a very simple, straightforward process to one that is complex and convoluted. During POST, the BIOS must integrate a plethora of competing, evolving, and even mutually exclusive standards and initiatives for the matrix of hardware and OSes the PC is expected to support. However, the average user still knows the POST and BIOS only through its simple visible memory tests and setup screen.
In the case of the IBM PC compatible machines, the main BIOS is divided into two basic sections. The POST section, or POST code, is responsible for the tasks mentioned above, and the environment POST constructs for the OS is known as the run-time code, the run-time BIOS, or the run-time footprint. Primarily these two divisions can be distinguished in that POST code should be flushed from memory before control is passed to the target OS while the run-time code remains resident in memory. This division may be a misleading oversimplification, however, as many Run-time functions are executed while the system is Posting.
The original IBM BIOS reported errors detected during POST by outputting a number to a fixed I/O port address, 80. Using a logic analyzer or a dedicated POST card, an interface card that shows port 80 output on a small display, a technician could determine the origin of the problem. (Note that once an operating system is running on the computer, the code displayed by such a board is often meaningless, since some OSes, e.g. Linux, use port 80 for I/O timing operations.) In later years, BIOS vendors used a sequence of beeps from the motherboard-attached loudspeaker to signal error codes.
These POST beep codes are covered specifically on the CompTIA A+ Core Hardware Exam:

Apple's Macintosh computers also perform a POST after a cold boot. In the event of a fatal error, the Mac will not make its start-up chime.
Old World Macs (until 1998)
Macs made prior to 1998, upon failing the POST, will immediately halt with a "death chime," which is a sound that varies by model; it can be a beep, a car crash sound, the sound of shattering glass, a short musical tone, or more. On the screen will be the Sad Mac icon, along with two hexadecimal strings, which can be used to identify the problem.
New World Macs (1998-1999)
When Apple introduced the iMac in 1998, it was a radical departure from other Macs of the time. The iMac began the production of New World Macs, as they are called; New World Macs, such as the iMac, Power Macintosh G3 (Blue & White), Power Mac G4 (PCI Graphics), PowerBook G3 (bronze keyboard), and PowerBook G3 (FireWire), load the Mac OS ROM from the hard drive. In the event of a fatal error, they give these beeps:
New World Macs (1999 onward) and Intel-based Macs
The beep codes were revised in October 1999, and have been the same since. In addition, on some models, the power LED would flash in cadence.